There are a number of different types of semiconductor based imagers, including charge coupled devices (CCDs), photodiode arrays, charge injection devices, hybrid focal arrays, etc. CCD technology is often employed for image acquisition and enjoys a number of advantages which makes it the preferred technology, particularly for small size imaging applications. CCDs are capable of large formats with small pixel size and they employ low noise charge domain processing techniques.
However, CCD imagers also suffer from a number of disadvantages. For example, they are susceptible to radiation damage, exhibit destructive readout over time, they require good light shielding to avoid image smear and they have a high power dissipation for large arrays. Additionally, while offering high performance, CCD arrays are difficult to integrate with CMOS processing in part due to a different processing technology and to their high capacitances, complicating the integration of on-chip drive and signal processing electronics with the CCD array. While there have been some attempts to integrate on-chip signal processing with CCD arrays, these attempts have not been entirely successful.
CCDs also must transfer an image by line charge transfers from pixel to pixel, requiring that the entire array be read out into a memory before individual pixels or groups of pixels can be accessed and processed. This takes a certain amount of time. CCD arrays may also suffer from incomplete charge transfer from pixel to pixel which results in image smear.
Because of the inherent limitations in CCD technology, there is an interest in complimentary metal oxide semiconductor (CMOS) imagers for possible use as low cost imaging devices. A fully compatible CMOS sensor technology enabling a higher level of integration of an image array with associated processing circuits would be beneficial to many digital applications such as, for example, in cameras, scanners, machine vision systems, vehicle navigation systems, video telephones, computer input devices, surveillance systems, auto focus systems, star trackers, motion detection systems, image stabilization systems and data compression systems for high-definition television.
Some of the advantages of CMOS imagers over CCD imagers are that CMOS imagers have a low voltage operation and low power consumption; CMOS imagers are compatible with integrated on-chip electronics (control logic and timing, image processing, and signal conditioning such as A/D conversion); CMOS imagers allow random access to the image data; and CMOS imagers have lower fabrication costs as compared with the conventional CCD because standard CMOS processing techniques can be used. Additionally, low power consumption is achieved for CMOS imagers because only one row of pixels at a time needs to be active during the readout and there is no charge transfer (and associated switching) from pixel to pixel during image acquisition. On-chip integration of electronics is particularly advantageous because of the potential to perform many signal conditioning functions in the digital domain (versus analog signal processing) as well as to achieve a reduction in system size and cost.
Among the challenges to employing CMOS for imager applications, is creating a structure which scales well but yet does not increase power consumption. One problem with conventional CMOS imagers is that pixel density cannot be increased on a CMOS chip without increasing power consumption due to increases in the size of the required decoder structure. A conventional approach to decoding an address space is to generate each address with an individual decoder. Consequently, as an address space increases, the decoder size increases as well since the number of bits requiring decoding increases. In the case of image sensors, the width of the decoder is fixed (decided by bit-size or number of pixels), and the only existing approach to add more bits into the decoder is to increase the decoder size which results in increases to the silicon area within which it can be implemented. Increases in silicon area brings with it increases in parasitic capacitance which results in slower circuits and increased power consumption. Consequently, a new approach to decoding an address space is needed for CMOS imagers to enable designers to increase address space while reducing power consumption and silicon area usage.